Integrated circuit chips are often subjected to physical attacks, such as live hardware analysis, aimed at gaining knowledge of the internal functioning of the chip and consequently influencing the operation of the chip. During such an attack, the plastic housing protecting the chip against mechanical damage may be opened on its top face to reveal a passivation layer covering the electronic circuitry. The passivation layer may be selectively removed by etching methods using laser, or Focused Ion Beam (FIB) technology, or using chemical means to allow access to the signal lines. Live hardware analysis techniques may be performed on integrated circuit chips during their operation, whereas other techniques such as reverse engineering, which is aimed at analyzing and reconstructing the operation of the chip, usually result in the destruction of the chip.
An analysis of the integrated circuit chip is usually undesirable. Live hardware analysis should be prevented, if possible, particularly in the case of secure circuits such as a microprocessor on a smart card including an electronic wallet function or the like. In practice, various methods already exist to render such an analysis more difficult. In general, an integrated circuit chip is formed by a plurality of stacked layers of semiconductor components and tracks. Each layer may include metallic planes or a plurality of tracks mainly for powering, which may also act as a physical shield. The top surface of the chip is in general covered by a passivation layer used for redundant power distribution and/or for providing physical shielding. An attacker may create openings in one or more of these layers for injecting faults in the circuits or capturing signals for analysis.
Physical attacks of all or parts of the chip may be prevented by so-called passive shields, such as metallic planes or tracks connected to a circuit configured to perform analogue integrity measurements in order to detect cuts, short circuits or capacitive load variations for example. The passive shield may be defeated by deviating tracks in an outside circuit or because of ineffective preset tolerance thresholds in the case of capacitive loads measurements.
Therefore, an active shield may be preferred. It may consist of a plurality of tracks arranged on the top of the chip in which random bit sequences are injected and checked for conformity from one end of a track to another. This active shield may be defeated by methods using a Focused Ion Beam (FIB) apparatus if the functions of the tracks are known and if their geometrical arrangement may be modified without altering the signals carried by the concerned tracks.
Document US2008/313746A1 discloses a protection circuit for integrity monitoring of an electronic device. The protection circuit includes: a first grid check line interleaved between a first set of conductor lines, each distributing a first potential reference to the electronic device, a second grid check line interleaved between a second set of conductor lines, each distributing a second potential reference to the electronic device, and a grid check circuit coupled to the first and second grid check lines. The first and second grid check lines are configured to provide first and second voltage references, respectively, to the grid check circuit for monitoring the integrity of the electronic device. According to an exemplary embodiment, the top two layers of metal of an integrated circuit are utilized. Most high performance sub-micron processes utilize 7-8 layers of metal and the top two layers are typically used for power distribution, clock distribution and assembly. A grid check line that runs parallel in each layer to the power grid is mixed within the top two layers of metal. The grid check lines are configured to be stimulated and sensed by grid check circuits located at various places around the die, preferably shielded by overlaying metal layers. The grid check circuits are configured to both stimulate the grid check lines as well as sense them. This allows the grid to be verified from multiple locations around the die with an active send/receive capability.